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cy2304 3.3 v zero delay buffer cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-07247 rev. *l revised february 25, 2014 3.3 v zero delay buffer features zero input-output propagation delay, adjustable by capacitive load on fbk input multiple configurations multiple low-skew outputs 10 mhz to 133 mhz operating range 90 ps typical peak cycle-to-cycle jitter at 15 pf, 66 mhz space-saving 8-pin 150-mil small outline integrated circuit (soic) package 3.3 v operation industrial temperature available functional description the cy2304 is a 3.3 v zero delay buffer designed to distribute high-speed clocks in pc, workst ation, datacom, telecom, and other high performance applications. the part has an on-chip phase-lo cked loop (pll) that locks to an input clock presented on the ref pin. the pll feedback is required to be driven into the fbk pin, and can be obtained from one of the outputs. the input-t o-output skew is guaranteed to be less than 250 ps, and output-to-output skew is guaranteed to be less than 200 ps. the cy2304 has two banks of two outputs each. the cy2304 pll enters a power down state when there are no rising edges on the ref input. in this mode, all outputs are three-stated and the pll is turned off, resulting in less than 25 ? a of current draw. multiple cy2304 devices can a ccept the same input clock and distribute it in a system. in this case, the skew between the outputs of two devices is guara nteed to be less than 500 ps. the cy2304 is available in two different configurations, as shown in available configurations . the cy2304-1 is the base part, where the output frequencies equal the reference if there is no counter in the feedback path. the cy2304-2 allows the user to obtain ref and 1/2x or 2x frequencies on each output b ank. the exact configuration and output frequencies depends on wh ich output drives the feedback pin. pll clka1 clka2 clkb1 ref clkb2 /2 extra divider (-2) fbk logic block diagram available configurations device fbk from bank a frequency bank b frequency cy2304-1 bank a or b reference reference cy2304-2 bank a reference reference/2 cy2304-2 bank b 2 reference reference
cy2304 document number: 38-07247 rev. *l page 2 of 17 contents pin configurations ........................................................... 3 pin definitions .................................................................. 3 zero delay and skew control .......................................... 4 maximum ratings ............................................................. 5 operating conditions ....................................................... 5 electrical characteristics ................................................. 5 switching characteristics ................................................ 6 operating conditions ....................................................... 7 electrical characteristics ................................................. 7 switching characteristics ................................................ 8 switching waveforms ...................................................... 9 ordering information ...................................................... 11 ordering code definitions ......................................... 11 package diagram ............................................................ 12 acronyms ........................................................................ 13 document conventions ................................................. 13 units of measure ....................................................... 13 appendix: silico n errata for the zero delay clock buffers, cy2304 ........ ............ ..... 14 part numbers affected .............................................. 14 cy2304 errata summary ........ ............... ........... ........ 14 cy2303 qualification status of fixed silicon .............. 14 document history page ................................................. 16 sales, solutions, and legal information ...................... 17 worldwide sales and design s upport ......... .............. 17 products .................................................................... 17 psoc? solutions ...................................................... 17 cypress developer community ................................. 17 technical support ................. .................................... 17
cy2304 document number: 38-07247 rev. *l page 3 of 17 pin configurations figure 1. 8-pin soic pinout 1 2 3 4 5 8 7 6 ref clka1 clka2 gnd v dd fbk clkb1 clkb2 pin definitions 8-pin soic pin signal description 1 ref [1] input reference frequency, 5 v tolerant input 2 clka1 [2] clock output, bank a 3 clka2 [2] clock output, bank a 4 gnd ground 5 clkb1 [2] clock output, bank b 6 clkb2 [2] clock output, bank b 7v dd 3.3 v supply 8 fbk pll feedback input notes 1. weak pull-down. 2. weak pull-down on all outputs.
cy2304 document number: 38-07247 rev. *l page 4 of 17 zero delay and skew control figure 2. ref. input to clka/clkb delay vs. difference in loading between fbk pin and clka/clkb pins to close the feedback loop of the cy2304, the fbk pin can be dr iven from any of the four availa ble output pins. the output driv ing the fbk pin is driving a total load of 7 pf, with any additional load that it drives. the relati ve loading of this output (with respect to the remaining outputs) can adjust the inpu t-output delay. this is shown in figure 2 . for applications requiring zero in put-output delay, all outputs including the one providing feedback must be equally loaded. if input-output delay adjustments are required, use the graph shown in figure 2 to calculate loading differences between the feedback output and remaining outputs. for zero output-output skew, be sure to load outputs equally. fo r further information on using cy2304, refer to the application note an1234 ?cy2308: zero delay buffer?.
cy2304 document number: 38-07247 rev. *l page 5 of 17 maximum ratings supply voltage to ground potential ............. ?0.5 v to +7.0 v dc input voltage (except ref) ........... ?0.5 v to v dd + 0.5 v dc input voltage ref ............... .............. ......... ?0.5 v to 7 v storage temperature ............................... ?65 c to +150 c junction temperature ................................................ 150 c static discharge voltage (per mil-std-883, method 3015) ........... .............. > 2000 v operating conditions for cy2304sxc commercial temperature devices parameter description min max unit v dd supply voltage 3.0 3.6 v t a operating temperature (ambient temperature) 0 70 c c l load capacitance (below 100 mhz) ? 30 pf load capacitance (from 100 mhz to 133 mhz) ? 15 pf c in input capacitance [3] ?7pf t pu power-up time for all v dd s to reach minimum specified voltage (power ramps must be monotonic) 0.05 50 ms electrical characteristics for cy2304sxc commercial temperature devices parameter description test conditions min max unit v il input low voltage ? 0.8 v v ih input high voltage 2.0 ? v i il input low current v in = 0 v ? 50.0 ? a i ih input high current v in = v dd ? 100.0 ? a v ol output low voltage [4] i ol = 8 ma (-1, -2) ? 0.4 v v oh output high voltage [4] i oh = ?8 ma (-1, -2) 2.4 ? v i dd (pd mode) power-down supply current ref = 0 mhz ? 12.0 ? a i dd supply current unloaded outputs, 100 mhz ref, select inputs at v dd or gnd ?45.0ma unloaded outputs, 66 mhz ref (-1, -2) ? 32.0 ma unloaded outputs, 33 mhz ref (-1, -2) ? 18.0 ma notes 3. applies to both ref clock and fbk. 4. parameter is guaranteed by design and charac terization. not 100% tested in production.
cy2304 document number: 38-07247 rev. *l page 6 of 17 switching characteristics for cy2304sxc commercial temperature devices parameter [5] name test conditions min typ max unit t 1 output frequency 30 pf load, all devices 10 ? 100 mhz t 1 output frequency 15 pf load, -1, -2 devices 10 ? 133.3 mhz t dc duty cycle [6] = t 2 ?? t 1 (-1, -2) measured at 1.4 v, f out = 66.66 mhz, 30-pf load 40.0 50.0 60.0 % t dc duty cycle [6] = t 2 ?? t 1 (-2) measured at 1.4 v, f out = 83.0 mhz, 15-pf load 40.0 50.0 60.0 % t dc duty cycle [6] = t 2 ?? t 1 (-1, -2) measured at 1.4 v, f out < 50 mhz, 15-pf load 45.0 50.0 55.0 % t 3 rise time [6] (-1, -2) measured between 0.8 v and 2.0 v, 30-pf load ? ? 2.20 ns t 3 rise time [6] (-1, -2) measured between 0.8 v and 2.0 v, 15-pf load ? ? 1.50 ns t 4 fall time [6] (-1, -2) measured between 0.8 v and 2.0 v, 30-pf load ? ? 2.20 ns t 4 fall time [6] (-1, -2) measured between 0.8 v and 2.0 v, 15 pf load ? ? 1.50 ns t 5 output-to-output skew on same bank (-1, -2) [6] all outputs equally loaded ? ? 200 ps output bank a to output bank b skew (-1) all outputs equally loaded ? ? 200 ps output bank a to output bank b skew (-2) all outputs equally loaded ? ? 400 ps t 6 skew, ref rising edge to fbk rising edge [6] measured at v dd /2 ? 0 ? 250 ps t 7 device-to-device skew [6] measured at v dd /2 on the fbk pins of devices ? 0 500 ps t j cycle-to-cycle jitter [6] (-1) measured at 66.67 mhz, loaded outputs, 15-pf load ? 90 175 ps measured at 66.67 mhz, loaded outputs, 30-pf load ? ? 200 ps measured at 133.3 mhz, loaded outputs, 15-pf load ? ? 100 ps t j cycle-to-cycle jitter [6] (-2) measured at 66.67 mhz, loaded outputs 30-pf load ? ? 400 ps measured at 66.67 mhz, loaded outputs 15-pf load ? ? 375 ps t lock pll lock time [6] stable power supply, valid clocks presented on ref and fbk pins ? ? 1.0 ms notes 5. all parameters are specified with loaded output. 6. parameter is guaranteed by design and charac terization. not 100% tested in production.
cy2304 document number: 38-07247 rev. *l page 7 of 17 operating conditions for cy2304sxi industrial temperature devices parameter description min max unit v dd supply voltage 3.0 3.6 v t a operating temperature (ambient temperature) ?40 85 c c l load capacitance (below 100 mhz) ? 30 pf load capacitance (from 100 mhz to 133 mhz) ? 15 pf c in input capacitance ? 7 pf electrical characteristics for cy2304sxi industrial temperature devices parameter description test conditions min max unit v il input low voltage ? 0.8 v v ih input high voltage 2.0 ? v i il input low current v in = 0 v ? 50.0 ? a i ih input high current v in = v dd ? 100.0 ? a v ol output low voltage [7] i ol = 8 ma (-1, -2) ? 0.4 v v oh output high voltage [7] i oh = ?8 ma (-1, -2) 2.4 ? v i dd (pd mode) power-down supply current ref = 0 mhz ? 25.0 ? a i dd supply current unloaded outputs, 100 mhz, select inputs at v dd or gnd ?45.0ma unloaded outputs, 66 mhz ref (-1, -2) ? 35.0 ma unloaded outputs, 33 mhz ref (-1, -2) ? 20.0 ma note 7. parameter is guaranteed by design and charac terization. not 100% tested in production.
cy2304 document number: 38-07247 rev. *l page 8 of 17 switching characteristics for cy2304sxi industrial temperature devices parameter [8] name test conditions min typ max unit t 1 output frequency 30-pf load, all devices 10 ? 100 mhz t 1 output frequency 15-pf load, all devices 10 ? 133.3 mhz t dc duty cycle [9] = t 2 ?? t 1 (-1, -2) measured at 1.4 v, f out = 66.66 mhz, 30-pf load 40.0 50.0 60.0 % t dc duty cycle [9] = t 2 ?? t 1 (-2) measured at 1.4 v, f out = 83.0 mhz, 15-pf load 40.0 50.0 60.0 % t dc duty cycle [9] = t 2 ?? t 1 (-1, -2) measured at 1.4 v, f out < 50 mhz, 15-pf load 45.0 50.0 55.0 % t 3 rise time [9] (-1, -2) measured between 0.8 v and 2.0 v, 30-pf load ? ? 2.50 ns t 3 rise time [9] (-1, -2) measured between 0.8 v and 2.0 v, 15-pf load ? ? 1.50 ns t 4 fall time [9] (-1, -2) measured between 0.8 v and 2.0 v, 30-pf load ? ? 2.50 ns t 4 fall time [9] (-1, -2) measured between 0.8 v and 2.0 v, 15-pf load ? ? 1.50 ns t 5 output-to-output skew on same bank (-1, -2) [9] all outputs equally loaded ? ? 200 ps output bank a to output bank b skew (-1) all outputs equally loaded ? ? 200 ps output bank a to output bank b skew (-2) all outputs equally loaded ? ? 400 ps t 6 skew, ref rising edge to fbk rising edge [9] measured at v dd /2 ? 0 ? 250 ps t 7 device-to-device skew [9] measured at v dd /2 on the fbk pins of devices ? 0 500 ps t j cycle-to-cycle jitter [9] (-1) measured at 66.67 mhz, loaded outputs, 15-pf load ? ? 180 ps measured at 66.67 mhz, loaded outputs, 30-pf load ? ? 200 ps measured at 133.3 mhz, loaded outputs, 15-pf load ? ? 100 ps t j cycle-to-cycle jitter [9] (-2) measured at 66.67 mhz, loaded outputs, 30-pf load ? ? 400 ps measured at 66.67 mhz, loaded outputs, 15-pf load ? ? 380 ps t lock pll lock time [9] stable power supply, valid clocks presented on ref and fbk pins ? ? 1.0 ms notes 8. all parameters are specified with loaded output. 9. parameter is guaranteed by design and charac terization. not 100% tested in production.
cy2304 document number: 38-07247 rev. *l page 9 of 17 switching waveforms figure 3. duty cycle timing figure 4. all outputs rise/fall time figure 5. output-output skew figure 6. input-output skew figure 7. device-device skew t 1 t 2 1.4 v 1.4 v 1.4 v output t 3 3.3 v 0 v 0.8 v 2.0 v 2.0 v 0.8 v t 4 1.4 v t 5 output output 1.4 v v dd /2 t 6 input fbk v dd /2 v dd /2 v dd /2 t 7 fbk, device 1 fbk, device 2
cy2304 document number: 38-07247 rev. *l page 10 of 17 figure 8. test circuit # 1 0.1 ? f v dd 0.1 ? f v dd clk out c load outputs gnd gnd test circuit for all parameters
cy2304 document number: 38-07247 rev. *l page 11 of 17 ordering code definitions ordering information ordering code package type operating range pb-free cy2304sxc-1 8-pin soic (150 mils) commercial CY2304SXC-1T 8-pin soic (150 mils) ? tape and reel commercial cy2304sxi-1 8-pin soic (150 mils) industrial cy2304sxi-1t 8-pin soic (150 mils) ? tape and reel industrial cy2304sxc-2 8-pin soic (150 mils) commercial cy2304sxc-2t 8-pin soic (150 mils) ? tape and reel commercial cy2304sxi-2 8-pin soic (150 mils) industrial cy2304sxi-2t 8-pin soic (150 mils) ? tape and reel industrial x = blank or t blank = tube; t = tape and reel x = 1 or 2 temperature range: x = c or i c = commercial; i = industrial x = pb-free package type: s = 8-pin soic base device part number company id: cy = cypress 2304 cy s x - x t x
cy2304 document number: 38-07247 rev. *l page 12 of 17 package diagram figure 9. 8-pin soic (150 mils) package outline, 51-85066 51-85066 *f
cy2304 document number: 38-07247 rev. *l page 13 of 17 acronyms document conventions units of measure acronym description pll phase locked loop soic small outline integrated circuit symbol unit of measure ? c degree celsius mhz megahertz a microampere ma milliampere ms millisecond ns nanosecond pf picofarad ps picosecond vvolt
cy2304 document number: 38-07247 rev. *l page 14 of 17 appendix: silicon errata for the zero delay clock buffers, cy2304 this section describes the errors, workaround solution and silicon design fixes for cypress zero delay clock buffers belonging to the families cy2304. details include errata trigger conditions, sco pe of impact, available workarounds, and silicon revision applic ability. contact your local cypress sales re presentative if you have questions. part numbers affected cy2304 errata summary cy2303 qualification status of fixed silicon product status: in production qualification report la st updated on 11/27/2012 http://www.cypre ss.com/?rid=72595 1. start up lock time issue problem definition output of cy2304 fails to locks within 1 ms upon power up (as per datasheet spec) parameters affected pll lock time trigger condition(s) start up scope of impact it can impact the performance of system and its throughput workaround apply reference input (refclk) before power up (v dd ). if refclk is applied after power up, noise gets coupled on the output and propagates back to the pll causing it to take higher time to acquire lock. if reference input is present during power up, noise will not propagate to the pll and device will start up normally without problems. fix status this issue is due to design marginality. two minor design modifications have been made to address this problem. a. addition of vco bias detector block as shown in the followi ng figure keeps comparator power down till vco bias is present and thereby eliminating the propagation of noise to feedback. b. bias generator enhancement for successful initialization. table 1. part numbers affected part number device variants cy2304sxc-1 all variants CY2304SXC-1T all variants cy2304sxc-2 all variants cy2304sxc-2t all variants cy2304sxi-1 all variants cy2304sxi-1t all variants cy2304sxi-2 all variants cy2304sxi-2t all variants items part number fix status start up lock time issue [cy2304] all silicon fixed. new silicon available from ww 10 of 2013
cy2304 document number: 38-07247 rev. *l page 15 of 17
cy2304 document number: 38-07247 rev. *l page 16 of 17 document history page document title: cy2304, 3.3 v zero delay buffer document number: 38-07247 rev. ecn orig. of change submission date description of change ** 110512 szv 12/11/01 change from spec number: 38-01010 to 38-07247 *a 112294 ckn 03/04/02 on pin configuration diagram (p.1), swapped clka2 and clka1 *b 113934 ckn 05/01/02 added operating conditions for cy2304si-x industrial temperature devices, p. 4 *c 121851 rbi 12/14/02 power up requirements added to operating conditions information *d 308436 rgl 01/26/05 added lead-free devices *e 2542331 aesa 09/18/08 updated template. added note ?not recommended for new designs.? removed part number cy2304si-2 and cy2304si-2t. changed lead-free to pb-free. changed idd (pd mode) from 12.0 to 25.0 ? a. deleted duty cycle parameters for f out < 50.0 mhz for commercial and industrial devices. *f 2673353 kvm / pyrs 03/13/09 reverted idd (pd mode) and duty cycle parameters back to the values in revision *d: changed idd (pd mode) from 25 to 12 ? a for commercial devices. added duty cycle parameters for f out < 50.0 mhz for commercial and industrial devices. *g 2906571 kvm 04/07/10 removed parts cy2304sc- 1, cy2304sc-1t, cy2304sc-2, cy2304sc-2t, cy2304si-1, cy2304si-1t from the ordering information table. updated package diagram. *h 3072674 bash 10/27/2010 corrected part number in all t able titles (pages 3 to 5) from cy2304sc-x and cy2304si-x to cy2304sxc and cy2304sxi. removed ?except t 8 ? from figure 7 *i 3162681 bash 02/04/2011 updated in new template. *j 3204827 cxq 03/24/201 1 added duty cycle spec for 83.0 mhz output condition. *k 4018186 cinm 06/10/2013 updated package diagram : spec 51-85066 ? changed revision from *d to *f. added appendix: silicon errata for the zero delay clock buffers, cy2304 . *l 4291190 cinm 02/25/2014 updated in new template. completing sunset review.
document number: 38-07247 rev. *l revised february 25, 2014 page 17 of 17 all products and company names mentioned in this document may be the trademarks of their respective holders. cy2304 ? cypress semiconductor corporation, 2001-2014. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc ? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support cypress.com/go/support

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